1. Field of the Invention
The present invention generally relates to data processing techniques and, in particular, to a system and method for performing a writing operation and a reading operation on a memory cell, such as a static-random-access-memory (SRAM) cell, during the same clock cycle.
2. Related Art
SRAM cells are known in the art for storing digital bit values and are used in many electronic applications requiring data storage, such as in the internal cache memory of a microprocessor. Each storage element within a SRAM cell usually stores only one bit of information at a time, and storing a new value into the storage element overwrites the previous value stored in the storage element.
In most conventional SRAM cells, only one value can be written to or read from the cell at a time. Therefore, during a single clock cycle, only a single operation may occur. As used herein, the term "operation" shall refer to a write to or a read from the memory cell that is being described. If there are two or more operations that are ready to occur, then at least one of the operations should be postponed until a later clock cycle such that no more than one operation occurs during each clock cycle. However, the postponement of operations is generally undesirable since it increases the amount of time required to produce the results of the operations.
U.S. Pat. No. 5,815,432, entitled "Single-Ended Read, Dual-Ended Write SRAM Cell," which is incorporated herein by reference, describes a design for a SRAM cell that enables a higher frequency of operations to occur. In this regard, the SRAM cell of the U.S. Pat. No. 5,815,432 enables two simultaneous reads of the same cell to occur. Therefore, during a single clock cycle, either two reads from an SRAM cell or one write to the SRAM cell may occur. As a result, the number of operations that utilize the same SRAM cell during a given time period is increased.
The design provided by U.S. Pat. No. 5,815,432 works well in applications that generate a large number of read operations. However, the advantages of the U.S. Pat. No. 5,815,432 are reduced in applications that utilize a large number of write operations, since the design of the U.S. Pat. No. 5,815,432 only enables read operations to simultaneously occur.
Thus, a heretofore unaddressed need exists in the industry for providing an SRAM cell that enables a write operation and a read operation to occur during the same clock cycle so that the number of write operations serviced during a particular time period can be increased.